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ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
FLASH MEMORY
FEATURES
* Thirty-nine erase blocks: Two 4K-word boot blocks (protected) Six 4K-word parameter blocks Thirty-one 32K-word main memory blocks * VCC, VCCQ and VPP voltages: 2.7V-3.3V VCC and VPP 2.7V-3.3V VCCQ* 5V VPP fast programming voltage * Address access times: 90ns, 110ns at 2.7V-3.3V * Low power consumption: Standby and deep power-down mode < 1A (typical ICC) Automatic power saving feature (APS mode) * Enhanced WRITE/ERASE SUSPEND (1s typical) * Industry-standard command set compatibility * Hardware block protection
MT28F160A3
Low Voltage, Extended Temperature
BALL ASSIGNMENT (Top View) 46-Ball FBGA
1 A B C D E F
A13
2
A11
3
A8
4
VPP
5
WP#
6
A19
7
A7
8
A4
A14
A10
WE#
RP#
A18
A17
A5
A2
A15
A12
A9
A6
A3
A1
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
VSS
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE#
OPTIONS
* Timing 90ns access 110ns access * Boot Block Starting Address Top (FFFFFH) Bottom (00000H) * Package 46-ball FBGA (6 x 8 ball grid) * Temperature Range Commercial (0C to +70C) Extended (-40C to +85C)
*Lower VCCQ ranges are available upon request.
Part Number Example:
NUMBER
(Ball Down)
-9 -11 T B FD None ET
NOTE: See page 3 for Ball Description Table. See last page for mechanical drawing.
MT28F160A3FD-11 TET
accomplished by using high voltage which can be supplied on a separate line. The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM), which simplifies these operations and relieves the system processor of secondary tasks. The WSM status can be monitored by an on-chip status register to determine the progress of program/erase tasks. Please refer to Micron's Web site (www.micron.com/ flash) for the latest data sheet.
GENERAL DESCRIPTION
The MT28F160A3 is a nonvolatile, electrically blockerasable (flash), programmable, read-only memory containing 16,777,216 bits organized as 1,048,576 words (16 bits). The MT28F160A3 is manufactured on 0.22m process technology in a 48-ball FBGA package. The device has an I/O supply of 2.7V (MIN). Programming in production is
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
DEVICE MARKING
Due to the size of the package, Micron's standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1.
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(c)2001, Micron Technology, Inc.
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
ARCHITECTURE
The MT28F160A3 flash contains eight 4K-word parameter blocks and thirty-one 32K-word blocks. The first two 4K-word blocks are called boot blocks and are locked with WP# control. Memory is organized by using a blocked architecture to allow independent erasure of selected memory blocks. Any address within a block address range selects that block for the required READ, WRITE, or ERASE operation (see Figures 1 and 2).
Table 1 Cross Reference for Abbreviated Device Marks1
PART NUMBER MT28F160A3FD-9 BET MT28F160A3FD-9 TET MT28F160A3FD-11 BET MT28F160A3FD-11 TET PRODUCT MARKING FW310 FW311 FW312 FW313 SAMPLE MARKING FX310 FX311 FX312 FX313
NOTE: 1. The mechanical sample marking is FY310.
FUNCTIONAL BLOCK DIAGRAM
DQ0-DQ15 X DEC Data Input Buffer Data Register RP# CE# WE# OE# Y/Z DEC Bank a Blocks Y/Z Gating/Sensing
ID Reg.
CSM
Status Reg.
WSM
Program/ Erase Change Pump Voltage Switch Output Multiplexer
DQ0-DQ15
Output Buffer
I/O Logic Data Comparator
A0-A19
Address Input Buffer
APS Control
Address CNT WSM Address Multiplexer
Y/Z DEC X DEC
Y/Z Gating/Sensing Bank b Blocks
Address Latch
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
BALL DESCRIPTIONS
46-BALL FBGA NUMBERS SYMBOL 3B WE# TYPE Input DESCRIPTION Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array. Write Protect: Unlocks the boot blocks when HIGH if VPP = 2.7V-3.3V or 5V (WRITE only) and RP# = VIH for WRITE or ERASE. Does not affect WRITE or ERASE operation on other blocks. Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. Reset/Power-Down: When LOW, RP# clears the status register, sets the write state machine (WSM) to the array read mode and places the device in deep power-down mode. All inputs, including CE#, are "Don't Care," and all outputs are High-Z. RP# must be held at VIH during all other modes of operation. Output Enable: Enables data output buffers when LOW. When OE# is HIGH, the output buffers are disabled. Address Inputs: These address inputs select a unique, 16-bit word out of the 1,048,576 available.
5A
WP#
Input
7D 4B
CE# RP#
Input Input
8F 1A, 1B, 1C, 1D, 2A, 2B, 2C, 3A, 3C, 5B, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C, 8D
OE# A0-A19
Input Input
2D, 2E, 2F, 3D, DQ0-DQ15 3E, 3F, 4D, 4E, 4F, 5D, 5E, 6D, 6E, 6F, 7E, 7F 4A VPP
Input/ Output
Data I/O: These data I/O are data output lines during any READ operation or data input lines during a WRITE. Data I/O are used to input commands to the CSM. Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until completion of the operation, VPP must be 2.7V-3.3V or 5V (WRITE only). VPP = "Don't Care" during all other operations. Power Supply: 2.7V-3.3V. I/O Supply Voltage: 2.7V-3.3V. Ground.
Supply
5F 1E 1F, 8E
VCC VCCQ VSS
Supply Supply Supply
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
TRUTH TABLE1
FUNCTION Standby RESET READING READ Output Disable WRITE/ERASE (EXCEPT BOOT BLOCKS)2 ERASE SETUP ERASE CONFIRM3 WRITE SETUP WRITE4 READ ARRAY5 WRITE/ERASE (BOOT ERASE SETUP ERASE CONFIRM3 WRITE SETUP WRITE4 READ ARRAY5 IDENTIFICATION6 H H H L L L L L L H H H X X X X X X L H H 2CH 90H 91H 00H 44H 44H DEVICE BLOCKS)2 H H H H H L L L L L H H H H H L L L L L X H X H X X VPPH X VPPH X X X X X X 20H D0H 10H/40H Data-In FFH X X X Data-In X H H H H H L L L L L H H H H H L L L L L X X X X X X VPPH X VPPH X X X X X X 20H D0H 10H/40H Data-In FFH X X X Data-In X H H L L L H H H X X X X X X Data-Out Data-Out High-Z High-Z RP# H L CE# H X OE# X X WE# X X WP# X X VPP X X A0 X X DQ0-DQ7 DQ8-DQ15 High-Z High-Z High-Z High-Z
Manufacturer Device (top boot) Device (bottom boot)
NOTE: 1. 2. 3. 4. 5. 6.
L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH ("Don't Care"). VPPH = 2.7V-3.3V for ERASE, and VPPH = 2.7V-3.3V or 5V for WRITE. Operation must be preceded by ERASE SETUP command. Operation must be preceded by WRITE SETUP command. The READ ARRAY command must be issued before reading the array after writing or erasing. See Table 3 for the IDENTIFY DEVICE command.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 1 Top Boot Block Memory Address Map
ADDRESS RANGE FFFFFh F8000h F7FFFh F0000h EFFFFh E8000h E7FFFh E0000h DFFFFh D8000h D7FFFh D0000h CFFFFh C8000h C7FFFh C0000h BFFFFh B8000h B7FFFh B0000h AFFFFh A8000h A7FFFh A0000h 9FFFFh 98000h 97FFFh 90000h 8FFFFh 88000h 87FFFh 80000h 7FFFFh 78000h 77FFFh 70000h 6FFFFh 68000h 67FFFh 60000h 5FFFFh 58000h 57FFFh 50000h 4FFFFh 48000h 47FFFh 40000h 3FFFFh 38000h 37FFFh 30000h 2FFFFh 28000h 27FFFh 20000h 1FFFFh 18000h 17FFFh 10000h 0FFFFh 08000h 07FFFh 00000h FFFFFh FF000h FEFFFh FE000h FDFFFh FD000h FCFFFh FC000h FBFFFh FB000h FAFFFh FA000h F9FFFh F9000h F8FFFh F8000h
8 x 4K-Word Blocks 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
4K-Word Block Parameter Blocks 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block
Boot Blocks
NOTE: 1. The two 4K-word blocks (boot blocks) can only be locked/unlocked by WP#.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 2 Bottom Boot Block Memory Address Map
ADDRESS RANGE FFFFFh F8000h F7FFFh F0000h EFFFFh E8000h E7FFFh E0000h DFFFFh D8000h D7FFFh D0000h CFFFFh C8000h C7FFFh C0000h BFFFFh B8000h B7FFFh B0000h AFFFFh A8000h A7FFFh A0000h 9FFFFh 98000h 97FFFh 90000h 8FFFFh 88000h 87FFFh 80000h 7FFFFh 78000h 77FFFh 70000h 6FFFFh 68000h 67FFFh 60000h 5FFFFh 58000h 57FFFh 50000h 4FFFFh 48000h 47FFFh 40000h 3FFFFh 38000h 37FFFh 30000h 2FFFFh 28000h 27FFFh 20000h 1FFFFh 18000h 17FFFh 10000h 0FFFFh 08000h 07FFFh 00000h
32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 32K-Word Block 8 x 4K-Word Blocks
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 07FFFh 07000h 06FFFh 06000h 05FFFh 05000h 04FFFh 04000h 03FFFh 03000h 02FFFh 02000h 01FFFh 01000h 00FFFh 00000h
Boot Blocks
4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block 4K-Word Block Parameter Blocks 4K-Word Block 4K-Word Block
NOTE: 1. The two 4K-word blocks (boot blocks) can only be locked/unlocked by WP#.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
MEMORY ORGANIZATION
The MT28F160A3 memory array is segmented into 31 blocks of 32K words, along with eight 4K-word parameter blocks. The device is available with block architecture mapped in either of the two configurations: the boot blocks located at the top or at the bottom of the memory array, as required by different microprocessors. The MT28F160A3 top boot configuration with the blocks and address ranges is shown in Figure 1 and the bottom boot configuration in Figure 2. The boot blocks are used to store key system data and are seldom changed during normal operation. When the WP# is at VIL , the contents of the boot block cannot be erased or reprogrammed. The boot block contents can be changed only through proper command sequences when WP# is HIGH (see Table 5).
OPERATION
Device operations are selected by entering standard JEDEC 8-bit command codes with conventional microprocessor timings into an on-chip CSM through I/Os DQ0-DQ7. When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. The on-chip status register allows the progress of various operations to be monitored. The status register is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1) and reading the register data on I/Os DQ0DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0-DQ7 (see Table 3).
COMMAND STATE MACHINE
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between the external microprocessor and the internal write state machine (WSM). The available commands are listed in Table 2, and the descriptions of these commands are shown in Table 3. Program and erase algorithms are automated by an on-chip WSM. Once a valid program/erase command sequence is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally to accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again.
Table 2 Command State Machine Codes for Device Mode Selection
COMMAND DQ0-DQ7 10h/40h 20h 50h 70h 90h B0h D0h FFh 60h, 0Fh, AFh CODE ON DEVICE MODE Write setup/alternate write setup Block erase setup Clear status register Read status register Identify device Program/erase suspend Program/erase resume Erase confirm Read array Reserved
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
COMMAND DEFINITIONS
Once a specific command code has been entered, the WSM executes an internal algorithm generating the necessary timing signals to program, erase, and verify data. See Table 3 for the CSM command definitions and data for each of the bus cycles.
Table 3 Command Definitions
FIRST CYCLE COMMAND READ ARRAY IDENTIFY DEVICE READ STATUS REGISTER WORD PROGRAM BLOCK ERASE PROGRAM/ERASE SUSPEND PROGRAM/ERASE RESUME CLEAR STATUS REGISTER
NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9.
SECOND CYCLE CSM/INPUT FFh 90h 70h 10h/40h 20h B0h D0h 50h OPERATION READ READ READ WRITE WRITE ADDRESS WA IA BA WA BA DATA AD ID SRD PD D0h
OPERATION WRITE WRITE WRITE WRITE WRITE WRITE WRITE WRITE
ADDRESS X X X X X X X X
The command data is written through DQ0-DQ7 ID = Manufacturer ID: 002Ch; Device ID (Top Boot): 4490h; Device ID (Bottom Boot): 4491h IA = Identify address: 00000h for manufacturer code and 00001h for device code BA = Any address within the block to be selected WA = Word address AD = Array data SRD = Data read from status register PD = Data to be written at location WA X = Don't Care
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
STATUS REGISTER
The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and by reading the resulting status code on I/Os DQ0-DQ7. The high-order I/Os (DQ8-DQ15) are set to 00h internally, so only the low-order I/Os (DQ0DQ7) need interpreting. Register data is updated on the falling edge of OE# or CE#. The latest falling edge of either of these two signals updates the latch within a given READ cycle. Latching the data prevents errors from occurring if the register input changes during a status register monitoring. To ensure that the status register output contains updated status data, CE# or OE# must be toggled for each subsequent STATUS READ. The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 4 defines the status register bits. After monitoring the status register during a PROGRAM/ERASE, the data appearing on DQ0-DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM.
CLEAR STATUS REGISTER
The WSM can set to "1" the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to internal operations. After issuing this command, the status bits are cleared and the device returns to the read array mode.
READ OPERATIONS
Three READ operations are available: read array, read device identification code, and read status register. READ ARRAY The array is read by entering the command code FFh on DQ0-DQ7. Control signals CE# and OE# must be at a logic LOW level (VIL) and WE# and RP# must be at a logic HIGH level (VIH) to read data from the array. Data is available on DQ0-DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial power-up, the device defaults to the read array mode. READ DEVICE IDENTIFICATION CODE Device identification codes are read by entering command code 90h on DQ0-DQ7. Two bus cycles are required for this operation, the first to enter the command code and the second to read the selected code. Control signals CE# and OE# must be at a logic LOW level (VIL) and WE# and RP# must be at a logic HIGH level (VIH). The manufacturer code is obtained on DQ0-DQ15 in the second cycle, after the identify address 00000h is latched. The device code is obtained on DQ0-DQ15 in the second cycle, after the identify address 00001h is latched (see Table 3). READ STATUS REGISTER The status register is read by entering the command code 70h on DQ0-DQ7. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RP# must be at a logic HIGH level (VIH). Two bus cycles are required for this operation: one to enter the command code, and one to read the status register. The status register contents are updated on the falling edge of CE# or OE#, whichever occurs last within the cycle.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for read, read device identification code, read status register, clear status register, program, erase, erase suspend, erase resume, program suspend, and program resume. The 8-bit command code is input to the device on DQ0-DQ7 (see Table 2 for CSM codes). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested. During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only. During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state until the microprocessor issues another command. The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range. For data protection, it is required that RP# be held at a logic LOW level during a CPU reset.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Table 4 Status Register
STATUS BIT # SR7 STATUS REGISTER BIT WRITE STATE MACHINE STATUS (WSM) 1 = Ready 0 = Busy ERASE SUSPEND STATUS 1 = ERASE SUSPEND 0 = ERASE in progress or ERASE complete ERASE STATUS 1 = BLOCK ERASE error 0 = BLOCK ERASE successful PROGRAM STATUS 1 = PROGRAM error 0 = PROGRAM successful VPP STATUS 1 = Program abort VPP range error 0 = VPP good PROGRAM SUSPEND STATUS 1 = PROGRAM suspended 0 = PROGRAM in progress or PROGRAM complete BLOCK LOCK STATUS 1 = Block locked 0 = Block not locked RESERVED DESCRIPTION If SR7 = 0 (busy), the WSM has not completed an ERASE or PROGRAM operation. If SR7 = 1 (ready), other operations can be performed. If SR6 = 1, WSM halts execution, indicating that the ERASE operation has been suspended. SR6 remains "1" until an ERASE RESUME command is issued. SR5 = 0 indicates that a BLOCK ERASE has been successful. SR5 = 1 indicates that an erase has failed; therefore, the WSM has completed the maximum allowable erase pulses determined by the internal algorithm but which were insufficient to completely erase the device. SR4 = 0 indicates successful programming has occurred at the address location. SR4 = 1 indicates the WSM was unable to correctly program the addressed location. SR3 provides status of VPP during programming.
SR6
SR5
SR4
SR3
SR2
If SR2 = 1, WSM halts execution, indicating the PROGRAM operation has been suspended. SR2 stays "1" until a PROGRAM RESUME command is issued. SR1 = 1 indicates that the address block is locked when WP# = VIL. Any attempt to program/erase this block will abort the operation and the device will return to read status mode.
SR1
SR0
NOTE: 1. After a PROGRAM/ERASE command is issued and confirmed, status bit SR7 goes LOW to indicate that the operation is in progress. If SR7 = 1 (ready), other polling operations can be performed. Until this occurs, the other status bits are not valid. SR7 is not updated automatically at the completion of a WSM task; therefore, if the WSM status bit shows busy (0), OE# and CE# must be toggled periodically to determine when the WSM has completed an operation (SR7 = 1). 2. When an ERASE SUSPEND command is issued, the WSM halts execution and sets SR6 = 1, indicating that the ERASE operation has been suspended. The WSM status bit is also set to HIGH (SR7 = 1), indicating that the ERASE SUSPEND operation has been completed successfully. 3. During an ERASE error, the SR5 bit is set (SR5 = 1), while SR5 = 0 indicates that a successful block erasure has occurred. 4. If the WSM is unable to program the addressed location correctly, the SR4 bit is set (SR4 = 1) and SR4 = 0 indicates that a successful programming operation has occurred at the addressed block location. Information concerning the status of VPP during programming/erasure is provided by SR3. If VPP is lower than VPPLK after a PROGRAM/ERASE command has been issued, SR3 is set to a "1," indicating that the PROGRAM/ERASE operation has aborted due to a low VPP. 5. During a PROGRAM SUSPEND command, the WSM halts execution and the SR2 bit is set, indicating that the PROGRAM operation has been suspended. This bit remains "1" until a PROGRAM RESUME command is issued. The WSM status bit is also set to HIGH (SR7 = 1), indicating that the PROGRAM SUSPEND operation has been completed successfully. 6. A proper block address must be provided in an ERASE operation. If that addressed block is protected, then the SR1 bit is set (SR1 = 1) when WP# = VIL. If that block is not protected, then SR1 = 0.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
PROGRAMMING OPERATIONS
There are two CSM commands for programming: program setup and alternate program setup (see Table 2). After the desired command code is entered, the WSM takes over and correctly sequences the device to complete the program operation. Monitoring of the WRITE operation is possible through the status register (see the Status Register section). During this time, the CSM responds only to a PROGRAM SUSPEND command until the PROGRAM operation has been completed, after which all commands to the CSM become valid again. (See Figure 3 for programming operation.) During programming, VPP must remain in the appropriate VPP voltage range as shown in the recommended operating conditions table. Different combinations of RP#, WP#, and VPP voltage levels ensure that data in certain blocks are secure and therefore cannot be programmed (see Table 5 for a list of combinations). Only "0s" are written and compared during a PROGRAM operation. If "1s" are programmed, the memory cell contents do not change and no error occurs. PROGRAM SUSPENSION The PROGRAM operation can be suspended by issuing a PROGRAM SUSPEND command (B0h). The PROGRAM SUSPEND command typically takes 1s to execute, and the device is then in program suspend mode. Once the WSM has reached the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER, and PROGRAM RESUME commands. During the PROGRAM SUSPEND operation, array data should be read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set. (See Figure 6 for PROGRAM SUSPEND and PROGRAM RESUME.)
ERASE OPERATIONS
An ERASE operation must be used to initialize all bits in an array block to "1s." After BLOCK ERASE CONFIRM is issued, the CSM responds only to an ERASE SUSPEND command until the WSM completes its task. Block erasure inside the memory array sets all bits within the addressed block to logic 1s. Erase is accomplished only by blocks; data at single address locations within the array cannot be erased individually. The block to be erased is selected by using any valid address within that block. Note that different combinations of RP#, WP# and VPP voltage levels ensure that data in certain blocks are secure and therefore cannot be erased (see Table 5 for a list of combinations). Block erasure is initiated by a command sequence to the CSM: block erase setup (20h) followed by block erase confirm (D0h) (see Figure 4). A two-command erase sequence protects against accidental erasure of memory contents. When the BLOCK ERASE CONFIRM command is complete, the WSM automatically executes a sequence of events to complete the block erasure. During this sequence, the block is programmed with logic 0s, data is verified, all bits in the block are erased, and finally verification is performed to ensure that all bits are correctly erased. Monitoring of the ERASE operation is possible through the status register (see the Status Register section). ERASE SUSPENSION During the execution of an ERASE operation, the ERASE SUSPEND command (B0h) can be entered to direct the WSM to suspend the ERASE operation. The ERASE SUSPEND command typically takes 1s to execute, and the device is then in erase suspend mode. Once the WSM has reached the suspend state, it allows the CSM to respond only to the READ ARRAY, READ STATUS REGISTER, ERASE RESUME and PROGRAM commands. Dur-
Table 5 Data Protection Combinations
DATA PROTECTION PROVIDED All blocks locked All blocks locked All blocks unlocked Boot blocks locked VPP VPPLK X VPPLK VPPLK RP# X VIL VIH VIH WP# X X VIH VIL
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
ing the ERASE SUSPEND operation, array data must be read from a block other than the one being erased. To resume the ERASE operation, an ERASE RESUME command (D0h) must be issued to cause the CSM to clear the suspend state previously set. It is also possible that an ERASE in any block can be suspended and a WRITE to another block can be initiated. After the completion of WRITE, the ERASE can be resumed by writing an ERASE RESUME command (see Figure 5). It is also possible to suspend the WRITE operation and read from another block. invalid or indeterminate, requiring that the operation be performed again after power restoration. When RP# is set at logic LOW, all internal circuits will be reset. Setting RP# LOW during a PROGRAM or ERASE operation is not recommended.
STANDBY MODE
ICC supply current is reduced by applying a logic HIGH level on CE# and RP# to enter the standby mode. In the standby mode, the outputs are placed in the high-impedance state. Applying a logic HIGH level (VCCQ) on CE# and RP# reduces the current to 1A typically. If the device is deselected during an ERASE operation or during programming, the device continues to draw active current until the operation is complete.
AUTOMATIC POWER-SAVING MODE
Substantial power savings are realized during periods when the device is not accessed while in the active mode. During this time, the device switches to the automatic power saving (APS) mode. When the device switches to this mode, ICC is reduced to 1A typically. This mode is entered automatically if no address or control lines toggle within approximately a 300ns time-out period. At least one transition on CE# must occur after power-up to activate this mode's availability. The device remains in this mode and the I/O lines retain the data from the last access until a new read address is issued or another operation is initiated.
BOOT BLOCK DATA PROTECTION
The WP# must be LOW for the locking mechanism to work. The only way to unlock boot blocks is to force the WP# signal HIGH. When WP# is LOW, the boot blocks are locked once again (see Table 5).
POWER-UP
During a power-up, it is not necessary to sequence VCCQ, VCC and VPP. However, it is recommended that RP# be held LOW during power-up for additional protection while VCC is ramping above VLKO to a stable operative level. After a power-up or RESET, the status register is reset, and the device will enter the array read mode. POWER-UP PROTECTION The likelihood of unwanted WRITE or ERASE operations is minimized since two consecutive cycles are required to execute either operation. When VCC < VLKO, the device does not accept any WRITE cycles, and noise pulses < 5ns on CE# or WE# do not initiate a WRITE cycle.
RESET/ DEEP POWER-DOWN MODE
Very low levels of power consumption can be attained by using a special ball, RP#, to disable internal device circuitry. When RP# is at a logic LOW level of 0.0V 0.2V, a much lower ICC current consumption is achieved, typically 1A. This is important in portable applications where extended battery life is a major concern. A recovery time is required when exiting from deep power-down mode. A minimum of tRS is required before a CSM command can be recognized. With RP# at ground, the WSM is reset and the status register is cleared, effectively eliminating accidental programming to the array during system reset. After restoration of power, the device will be disabled until RP# is returned to VIH . If RP# goes LOW during a PROGRAM or ERASE operation, the device powers down and becomes nonfunctional. Data being written or erased at that time becomes
POWER SUPPLY DECOUPLING
For decoupling purposes, each device should have a 0.1F ceramic capacitor connected between VCC and VSS, VPP and VSS, and between VCCQ and VSS. The capacitor should be as close as possible to the device balls.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 3 Automated Word Programming Flowchart
Start
BUS OPERATION COMMAND WRITE WRITE WRITE SETUP WRITE DATA
COMMENTS Data = 40h or 10h Addr = Don't Care Data = Word to be programmed Addr = Address of word to be programmed Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
Issue WRITE SETUP Command
READ
Issue Word Address and Word Data
Standby
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 PROGRAM SUSPEND? PROGRAM SUSPEND Loop
Repeat for subsequent words. Write FFh after the last word programming operation to reset the device to read array mode.
YES
Word Program Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND Standby
COMMENTS Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP low Check SR43 1 = Word program error
SR1 = 0? YES
NO PROGRAM Attempted on a Locked Block
Standby Standby
NO SR3 = 0? YES NO SR4 = 0? YES Word Program Passed
VPP Range Error
Word Program Failed
NOTE: 1. Full status register check can be done after each word or after a sequence of words. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation attempts.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
ADVANCE
1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 4 Automated BLOCK ERASE Flowchart
Start Issue ERASE SETUP Command
BUS OPERATION COMMAND WRITE WRITE ERASE SETUP ERASE
COMMENTS Data = 20h Addr = Don't Care Data = D0h Block Addr = Address within block to be erased Status register data Toggle OE# or CE# to update status register. Check SR7 1 = Ready, 0 = Busy
WRITE
Issue Block Address and ERASE CONFIRM Command
READ
Read Status Register Bits NO NO SR7 = 1? YES Full Status Register Check (optional)1 ERASE SUSPEND?
ERASE SUSPEND Loop
Standby
Repeat for subsequent blocks. Write FFh after the last BLOCK ERASE operation to reset the device to read array mode.
YES
BLOCK ERASE Completed FULL STATUS REGISTER CHECK FLOW Read Status Register Bits
BUS OPERATION COMMAND Standby
NO
COMMENTS Check SR1 1 = Detect locked block Check SR32 1 = Detect VPP low Check SR4 and SR5 1 = BLOCK ERASE command error Check SR53 1 = BLOCK ERASE error
SR1 = 0? YES NO SR3 = 0? YES SR4 = 1 and SR5 = 1? NO NO SR5 = 0? YES BLOCK ERASE Passed YES
ERASE Attempted on a Locked Block
Standby Standby
VPP Range Error
Standby
Command Sequence Error
BLOCK ERASE Failed
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks. 2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations. 3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full status is checked.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 5 ERASE SUSPEND/ERASE RESUME Flowchart
Start
BUS OPERATION COMMAND WRITE READ ERASE SUSPEND
COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register Check SR7 1 = Ready Check SR6 1 = Suspended
Issue ERASE SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE or WRITE READ
READ MEMORY WRITE SETUP
Data = FFh
NO SR7 = 1? YES NO SR6 = 1? YES ERASE Complete PROGRAM
Data = 40h or 10h Addr = Don't Care Read data from block other than that being erased
or WRITE
WRITE DATA
Data = Word to be programmed Addr = Address of word to be programmed Data = D0h Addr = Don't Care
WRITE
ERASE RESUME
READ or PROGRAM? READ Issue READ MEMORY Command
PROGRAM Loop
NO
READ or PROGRAM Complete? YES Issue ERASE RESUME Command
(Note 2)
ERASE Continued1
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure. 2. See Word Programming Flowchart for complete programming procedure.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Figure 6 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart
Start
BUS OPERATION COMMAND WRITE READ PROGRAM SUSPEND COMMENTS Data = B0h Status register data Toggle OE# or CE# to update status register Check SR7 1 = Ready Check SR2 1 = Suspended READ MEMORY Data = FFh Read data from block other than that being programmed PROGRAM RESUME Data = D0h Addr = Don't Care
Issue PROGRAM SUSPEND Command
Standby Standby
Read Status Register Bits
WRITE READ WRITE
NO SR7 = 1? YES NO SR2 = 1? YES Issue READ MEMORY Command PROGRAM Complete
Finished Reading ? YES Issue PROGRAM RESUME Command
NO
PROGRAM Resumed
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS1, 2
Supply Voltage Range, Supply Voltage Range, Input Voltage Range ................................... -0.6V to +4.0V Output Voltage Range .............................. -0.6V to +4.0V4 Storage Temperature Range, TSTG ........... -65C to +150C VCC ....................... -0.6V to +4.0V3 VPP ....................... -0.6V to +6.0V3
1Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2All voltage values are with respect to VSS. 3The voltage can undershoot to -1V for periods < 20ns. 4The voltage on any output can overshoot to 4.6V for periods < 20ns.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-40C TA +85C) PARAMETER/CONDITION Supply Voltage (during program/read/erase/suspend) I/O Supply Voltage Supply Voltage (during program/erase operations) Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs OUTPUT VOLTAGE LEVELS VCC = VCC (MIN), VCCQ = VCCQ (MIN) Output High Voltage (IOH = -0.1mA) Output Low Voltage (IOL = 0.1mA) INPUT LEAKAGE CURRENT VCC = VCC (MAX), VCCQ = VCCQ (MAX) Any input (0V VIN VCCQ); All other balls not under test = 0V OUTPUT LEAKAGE CURRENT VCC = VCC (MAX), VCCQ = VCCQ (MAX) (DOUT is disabled; 0V VOUT VCCQ) BLOCK ERASE cycling
NOTE: 5. All voltages referenced to VSS. 6. VCCQ must be less than or equal to VCC. 7. 5V VPP is allowable for production programming only, not erasing.
SYMBOL VCC VCCQ VPP1 VPP2 VIH VIL VOH VOL
MIN 2.7 2.7 2.7 5 -0.2 VCCQ - 0.1 -
MAX 3.3 3.3 3.3 5.5 0.2 - 0.1
UNITS NOTES V V V V V V V 5 V 5 5, 6 5 5, 7 5 5
VCCQ - 0.2 VCCQ + 0.2
IL
-1
1
A
IOZ -
-10 100K
10 -
A Cyc
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
CAPACITANCE
(TA = +25C; f = 1 MHz) PARAMETER/CONDITION Input Capacitance Output Capacitance SYMBOL CI CO MAX 8 12 UNITS NOTES pF pF
READ, STANDBY AND DEEP POWER-DOWN CURRENT DRAIN
(-40C TA +85C; VCC = 2.7V-3.3V) PARAMETER/CONDITION READ CURRENT: VCC = VCC (MAX), VCCQ = VCCQ (MAX) (CE# = VIL; OE# = VIH; RP# = VIH; f = 5 MHz; Other inputs VIH or VIL) STANDBY CURRENT: VCC SUPPLY VCC = VCC (MAX); (CE# = RP# = VCCQ) DEEP POWER-DOWN CURRENT: VCC SUPPLY VCC = VCC (MAX); VCCQ = VCCQ (MAX) (RP# = VIL; Other inputs VCCQ or VSS) READ CURRENT: VPP SUPPLY DEEP POWER-DOWN CURRENT: VPP SUPPLY (RP# = VIL; VPP VCC) VPP VCC VPP > VCC SYMBOL ICC1 ICC2 TYP - 1 MAX UNITS NOTES 20 10 mA A 1, 2
ICC3 IPP1 IPP2 IPP3
1 2 50 1
10 15 200 10
A A A A
NOTE: 1. ICC is dependent on cycle rates. 2. Automatic power savings (APS) mode reduces ICC1 to standby current level ICC2 for static operation.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
AC TEST CONDITIONS
Input pulse levels .................................................. 0V to VCCQ Input rise and fall times ................................................ <10ns Input timing reference level ....................................... VCCQ/2 Output timing reference level .................................... VCCQ/2 Output load ............................................................. CL = 30pF
Figure 7 AC Test Output and Load Circuit
0.1mA IOL
VCCQ 2 CL = 30pf
1
Output under test
-0.1mA
IOH
Figure 8 AC Input/Output Reference Waveform
VCCQ Input 0.0V VCCQ 2 VCCQ Output 2
Test Points
Test Points
NOTE: 1. CL includes probe and fixture capacitance.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
READ AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-40C TA +85C; VCC = 2.7V-3.3V; VCCQ = 2.7V-3.3V)
AC CHARACTERISTICS PARAMETER READ cycle time Access time from CE# Access time from OE# Access time from address RP# HIGH to output valid delay RP# LOW pulse width OE# or CE# HIGH to output in High-Z Output hold time from OE#, CE# or address change -9 SYMBOL tRC tACE tAOE tAA tRWH tRP tOD tOH MIN 90 MAX 90 30 90 600 100 25 0 0 100 25 MIN 110 -11 MAX 110 30 110 600 UNITS NOTES ns ns 1 ns 1 ns ns ns ns ns
NOTE: 1. OE# may be delayed by tACE minus tAOE after CE# falls before tACE is affected.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
READ CYCLE
VIH A0-A19 VIL VALID ADDRESS tRC tAA VIH CE# VIL tACE VIH OE# VIL VIH WE# VIL tOD tAOE VOH DQ0-DQ15 VOL tRWH VIH RP# VIL VALID DATA tOH
DON'T CARE UNDEFINED
TIMING PARAMETERS
-9 SYMBOL tRC tACE tAOE
tAA
MIN 90
MAX 90 30 90
MIN 110
-11 MAX 110 30 110
-9 UNITS ns ns ns ns SYMBOL tRWH tOD
tOH
MIN
MAX 600 25
MIN
-11 MAX 600 25
UNITS ns ns ns
0
0
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
RECOMMENDED DC WRITE/ERASE CONDITIONS
(-40C TA +85C; VCC = 2.7V-3.3V) PARAMETER/CONDITION VPP WRITE/ERASE lockout voltage VPP voltage during WRITE/ERASE operation VCC WRITE/ERASE lockout operation SYMBOL VPPLK VPPH VLKO MIN - 2.7 - TYP 2.0 - 1.5 MAX - 3.3 - UNITS NOTES V V V 1 2
WRITE/ERASE CURRENT DRAIN
(-40C TA +85C; VCC = 2.7V-3.3V; VPP = 2.7V-3.3V) PARAMETER/CONDITION WRITE CURRENT: VCC + VPP SUPPLY ERASE CURRENT: VCC + VPP SUPPLY ERASE/PROGRAM SUSPEND CURRENT: VPP SUPPLY (ERASE/PROGRAM suspended) SYMBOL ICC4 + IPP4 ICC5 + IPP5 IPP6 TYP - - 50 MAX 55 45 200 UNITS NOTES mA mA A 3 2
WORD WRITE AND ERASE DURATION CHARACTERISTICS
2.7V-3.3V Vcc 2.7V-3.3V VPP PARAMETER Boot/parameter BLOCK ERASE time Main BLOCK ERASE time Boot/parameter BLOCK WRITE time Main BLOCK WRITE time Program/erase suspend latency TYP 0.5 1.0 0.1 0.3 1 MAX 4 5 - - 3 5V VPP TYP - - 0.1 0.3 1 MAX UNITS NOTES - - - - 3 s s s s s 4, 5 4, 5 5, 6, 7 5, 6, 7
NOTE: 1. Absolute WRITE/ERASE protection when VPP VPPLK. 2. 5V VPP is allowable for production programming only, not erasing. Write timings are identical to 2.7V-3.3V VPP operation, and 5V VPP programming current is not greater than IPP4. 3. Parameter is specified when device is not accessed. Actual current draw will be IPP6 plus current of operation being executed while the device is in suspend mode. 4. The 5V VPP is for programming only, not erasing. 5. Typical values measured at TA = +25C. 6. Assumes no system overhead. 7. Typical write times tested with checkerboard data pattern.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
SPEED-DEPENDENT WRITE/ERASE AC TIMING CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS: WE# (CE#)-CONTROLLED WRITES
(-40C TA +85C; VCC = 2.7V-3.3V)
AC CHARACTERISTICS PARAMETER WE# (CE#) HIGH pulse width WE# (CE#) pulse width Address setup time to WE# (CE#) HIGH Address hold time from WE# (CE#) HIGH Data setup time to WE# (CE#) HIGH Data hold time from WE# (CE#) HIGH CE# (WE#) setup time to WE# (CE#) LOW CE# (WE#) hold time from WE# (CE#) HIGH VPP setup time to WE# (CE#) HIGH RP# HIGH to WE# (CE#) LOW delay WRITE duration Boot BLOCK ERASE duration Parameter BLOCK ERASE duration Main BLOCK ERASE duration VPP hold time from status data valid WE# (CE#) HIGH to busy status (SR7 = 0) SYMBOL tWPH (tCPH) tWP (tCP) tAS tAH tDS tDH tCS (tWS) tCH (tWH) tVPS tRS tWED1 tWED2 tWED3 tWED4 tVPH tWB -9 MIN 30 70 70 0 50 0 0 0 200 600 6 0.5 0.5 1 0 200 -11 MIN 30 70 70 0 60 0 0 0 200 600 6 0.5 0.5 1 0 200 UNITS ns ns ns ns ns ns ns ns ns ns s s s s ns ns NOTES
1, 2
NOTE: 1. Polling status register before tWB is met may falsely indicate WRITE or ERASE completion. 2. tWB = 800ns (MAX).
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE WE#-CONTROLLED WRITE/ERASE
VIH A0-A19 VIL VIH CE# VIL tCS VIH OE# VIL VIH WE# VIL tDS DQ0-DQ15 VIH VIL VIH RP# VIL VIH WP# VIL tVPS VPP VPPH VIL WRITE or block address asserted, and WRITE data or ERASE CONFIRM tVPH [Unlock boot blocks] tRS CMD in tWB tDH tDS CMD/ Data-in tDH Status (SR7=0) Status (SR7=1) CMD in tWP tWPH tWED1, 2, 3, 4 tCH Note 1 tAS tAH tAS AIN tAH
WRITE SETUP or ERASE SETUP input
WRITE or ERASE executed, status register checked for completion
Command for next operation issued
DON'T CARE
TIMING PARAMETERS
-9 MIN 30 70 70 0 50 0 0 0 -11 MIN 30 70 70 0 60 0 0 0 -9 MIN 200 600 6 0.5 0.5 1 0 200 -11 MIN 200 600 6 0.5 0.5 1 0 200
SYMBOL
tWPH tWP tAS tAH tDS tDH tCS tCH
UNITS ns ns ns ns ns ns ns ns
SYMBOL
tVPS tRS tWED1 tWED2 tWED3 tWED4 tVPH tWB2
UNITS ns ns s s s s ns ns
NOTE: 1. Address inputs are "Don't Care" but must be held stable. 2. tWB = 800ns (MAX).
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
WRITE/ERASE CYCLE CE#-CONTROLLED WRITE/ERASE
VIH A0-A19 VIL VIH WE# VIL tWS VIH OE# VIL VIH CE# VIL t WB tDS DQ0-DQ15 VIH VIL VIH RP# VIL VIH WP# VIL tVPS VPP VPPH VIL WRITE or block address asserted, and WRITE data or ERASE CONFIRM tVPH [Unlock boot blocks] tRS CMD in tDH tDS CMD/ Data-in tDH Status (SR7=0) Status (SR7=1) CMD in tCP tCPH tWED1, 2, 3, 4 tWH Note 1 tAS tAH tAS AIN tAH
WRITE SETUP or ERASE SETUP input
WRITE or ERASE executed, status register checked for completion
Command for next operation issued
DON'T CARE
TIMING PARAMETERS
-9 MIN 30 70 70 0 50 0 0 0 -11 MIN 30 70 70 0 60 0 0 0 -9 MIN 200 600 6 0.5 0.5 1 0 200 -11 MIN 200 600 6 0.5 0.5 1 0 200
SYMBOL tCPH
tCP tAS tAH tDS tDH tWS tWH
UNITS ns ns ns ns ns ns ns ns
SYMBOL tVPS
tRS tWED1 tWED2 tWED3 tWED4 tVPH tWB2
UNITS ns ns s s s s ns ns
NOTE: 1. Address inputs are "Don't Care" but must be held stable. 2. tWB = 800ns (MAX).
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
Table 6 Command State Machine Current/Next States
COMMAND INPUTS (and next state) Current State SR7 Data when Read Array Status ID Status Status Program (not complete) Program susp. read array Program susp. read array Read Array Program suspend read array Program Read Array (FFh) Read array Read array Read array Write setup (10h/ 40h) Write setup Write setup Write setup Block erase setup (20h) Erase setup Erase setup Erase setup Erase confirm (D0h) Prog./ erase susp. (B0h) Read array Read array Read array Program Prog. susp. status Program (not complete) Program suspend read array Program suspend read array Read array Identify device Prog./ erase resume (D0h) Read SR (70h) Read status Read status Read status Clear SR (50h) Read array Read array Read array Identify device (90h) Identify device Identify device Identify device
Read Array Read Status Identify Device Write Setup Program Not Complete Program Suspend Status Program Suspend Read Array Program Complete Erase Setup Erase Comd. Error Erase Not Complete Erase Suspend Status Erase Suspend Array Erase Complete
1 1 1 1 0
1
Status
Program Program Program susp. susp. read status array Program Program Program susp. susp. read status array Read array Read status Erase
1
Array
Program suspend read array
Program
1 1 1 0
Status Status Status Status
Write setup
Erase setup Erase
Erase command error Read array Write setup Erase setup
Erase Read array Erase susp. to status
Erase command error Read status Read array Identify device
Erase (not complete)
Erase (not complete)
1
Status
Erase susp. read array Erase susp. read array Read array
Write setup
Erase susp. read array Erase susp. read array Erase setup
Erase
Erase susp. read array Erase susp. read array Read array
Erase
Erase susp. status Erase susp. status Read status
Erase suspend read array
1
Array
Write setup
Erase
Erase
Erase suspend read array
1
Status
Write setup
Read array
Identify device
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
46-BALL FBGA
.80 .075
.10
A
A
5.25 .75 (TYP)
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: O .27mm SUBSTRATE: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC PIN #1 ID PIN #1 ID
O .35 +.05 (TYP) -.10
3.50 .05 7.00 .10 1.875 .05
.75 (TYP) 3.75
2.625 .05
4.00 .05
8.00 .10
1.20 MAX
NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
DATA SHEET DESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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1 MEG x 16 ENHANCED BOOT BLOCK FLASH MEMORY
REVISION HISTORY
Rev. 3 .................................................................................................................................................................................... 8/01 * Added tWB maximum specification * Corrected WRITE/ERASE Cycle timing diagram (CE-controlled) Rev. B ................................................................................................................................................................................... 5/01 * Changed ICC1 MAX from 30 mA to 20 mA Original document ............................................................................................................................................................. 6/00
1 Meg x 16 Enhanced Boot Block Flash Memory MT28F160A3_3.p65 - Rev. 3, Pub. 8/01
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2001, Micron Technology, Inc.

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